NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 644

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NH82801FBM S L89K

Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FBM S L89K

Lead Free Status / RoHS Status
Compliant
Intel
18.1.35
18.1.36
18.1.37
644
®
High Definition Audio Controller Registers (D27:F0)
PVCCAP1—Port VC Capability Register 1
(Intel
Address Offset:
Default Value:
PVCCAP2—Port VC Capability Register 2
(Intel
Address Offset:
Default Value:
PVCCTL—Port VC Control Register
(Intel
Address Offset:
Default Value:
31:12
11:10
31:24
23:8
15:4
Bit
9:8
6:4
2:0
Bit
7:0
Bit
3:1
7
3
0
®
®
®
Reserved.
Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device.
Reference Clock — RO. Hardwired to 0 since this is an endpoint device.
Reserved.
Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs to the low
priority VC group
Reserved.
Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in addition to VC0) is
supported by the Intel High Definition Audio controller.
VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table is not
present.
Reserved.
VC Arbitration Capability — RO. Hardwired to 0. These bits are not applicable since the Intel High
Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1
register.
Reserved.
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However, these bits are
not applicable since the Intel High Definition Audio controller reports a 0 in the Low Priority Extended
VC Count bits in the PVCCAP1 register
Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not present.
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
104h
00000001h
108h
00000000h
10Ch
0000h
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
32 bits
32 bits
16 bits
RO
RO
RO

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