NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 257

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

7.1.23
7.1.24
7.1.25
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
ILCL—Internal Link Capabilities List Register
Offset Address:
Default Value:
LCAP—Link Capabilities Register
Offset Address:
Default Value:
LCTL—Link Control Register
Offset Address:
Default Value:
31:20
19:16
31:18
17:15
14:12
11:10
15:0
15:8
Bit
Bit
9:4
3:0
Bit
6:2
1:0
7
Next Capability Offset (NEXT) — RO. This field indicates this is the last item in the list.
Capability Version (CV) — RO. This field indicates the version of the capability structure.
Capability ID (CID) — RO. This field indicates this is capability for DMI.
Reserved
L1 Exit Latency (EL1) — L1 not supported on DMI.
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to less than 256
ns.
Active State Link PM Support (APMS) — R/WO. This field indicates that L0s is supported on DMI.
Maximum Link Width (MLW) — This field indicates the maximum link width is 4 ports.
Maximum Link Speed (MLS) — This field indicates the link speed is 2.5 Gb/s.
Reserved
Extended Synch (ES) — R/W. When set, forces extended transmission of FTS ordered sets
when exiting L0s prior to entering L0.
Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI should enter
L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
01A0–01A3h
00010006h
01A4–01A7h
00012441h
01A8–01A9h
0000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
RO
32-bit
RO, R/WO
32-bit
R/W
16-bit
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