NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 222

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.21.7.1
.
222
Table 5-51. Slave Write Registers
Table 5-52. Command Types (Sheet 1 of 2)
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH6 SMBus slave interface. The
“Command” field (bits 11
indicate the value that should be written to that register.
the registers.
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data
Command
Type
Register
9–FFh
0
1
2
3
4
5
6
7
1–3
6–7
byte registers until they have been read by the system processor. The ICH6 overwrites the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH6 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
0
4
5
8
Reserved
WAKE/SMI#. This command wakes the system if it is not already awake. If system is already
awake, an SMI# is generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same
effect as the Powerbutton Override occurring.
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does
not include cycling of the power supply). This is equivalent to a write to the CF9h register with
bits 2:1 set to 1, but bit 3 set to 0.
HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of
the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.
Disable the TCO Messages. This command will disable the Intel
Heartbeat and Event messages (as described in
executed, Heartbeat and Event message reporting can only be re-enabled by assertion and de-
assertion of the RSMRST# signal.
WD RELOAD: Reload watchdog timer.
Reserved
Command Register. See
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Reserved
Reserved
awake. The SMI handler should then clear this bit.
:
18) indicate which register is being accessed. The Data field (bits 20
Table 5-52
Intel
®
below for legal values written to this register.
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Function
Table 5-51
Section
5.15.2). Once this command has been
has the values associated with
®
ICH6 from sending
:
27)