NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 66

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Signal Description
66
Table 2-12. Power Management Interface Signals (Sheet 2 of 2)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
MCH_SYNC#
SUS_STAT# /
VRMPWRGD
DPRSLPVR
LAN_RST#
STP_CPU#
BATLOW#
STP_PCI#
BMBUSY#
DPRSTP#
SUSCLK
LPCPD#
GPO[18]
GPO[20]
WAKE#
GPI[6]
Name
TP[0]
TP[1]
TP[4]
Type
O
O
O
O
O
O
I
I
I
I
I
I
LAN Reset: When asserted, the internal LAN controller will be put into reset. This
signal must be asserted for at least 10 ms after the resume well power (VccSus3_3
and VccSus1_5 in desktop and VccLAN3_3 and VccLAN1_5 in mobile) is valid.
When de-asserted, this signal is an indication that the resume (LAN for mobile) well
power is stable.
NOTE: LAN_RST# must de-assert at some point to complete ICH6 power up
PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by
components requesting wakeup.
MCH SYNC: This input is internally ANDed with the PWROK input.
Desktop: Connected to the ICH_SYNC# output of (G)MCH.
Mobile: Refer to the Platform Design Guide.
Suspend Status: This signal is asserted by the ICH6 to indicate that the system will
be entering a low power state soon. This can be monitored by devices with memory
that need to switch from normal refresh to suspend refresh mode. It can also be
used by other peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on the LPC I/F.
Suspend Clock: This clock is an output of the RTC generator circuit to be used by
other chips for refresh clock.
VRM Power Good: This should be connected to be the processor’s VRM Power
Good signifying the VRM is stable. This signal is internally ANDed with the PWROK
input.
Bus Master Busy: To support the C3 state. Indication that a bus master device is
busy. When this signal is asserted, the BM_STS bit will be set. If this signal goes
active in a C3 state, it is treated as a break event.
NOTES:
Stop PCI Clock: This signal is an output to the external clock generator for it to turn
off the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is
not needed, this signal can be configured as a GPO.
Stop Processor Clock: This signal is an output to the external clock generator for it
to turn off the processor clock. It is used to support the C3 state. If this functionality
is not needed, this signal can be configured as a GPO.
Battery Low: This signal is an input from battery to indicate that there is insufficient
power to boot the system. Assertion will prevent wake from S3–S5 state. This signal
can also be enabled to cause an SMI# when asserted.
Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM
during the C4 state. When the signal is high, the voltage regulator outputs the lower
“Deeper Sleep” voltage. When low (default), the voltage regulator outputs the higher
“Normal” voltage.
Deeper Sleep: This is a copy of the DPRSLPVR and it is active low.
1. This signal is internally synchronized using the PCICLK and a two-stage
2. In desktop configurations, this signal is a GPI.
synchronizer. It does not need to meet any particular setup or hold time.
sequencing.
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Description