NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 463

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.1.15
12.1.15.1
12.1.15.2
12.1.16
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
ABAR — AHCI Base Address Register
(SATA–D31:F2)
Intel
Address Offset:
Default Value:
Note: For ICH6, this register is Reserved and Read Only, unless the SCRAE bit (offset 94h:bit 9) is
set, in which case the register follows the definition given in
Intel
Address Offset:
Default Value:
This register allocates space for the memory registers defined in
NOTES:
SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset:
Default Value:
Lockable:
1. When the MAP.MV register is programmed for combined mode (00b), this register is RO. Software is
2. The ABAR register must be set to a value of 0001_0000h or greater.
31:10
15:0
31:0
Bit
Bit
Bit
9:4
2:1
responsible for clearing this bit before entering combined mode.
3
0
®
®
ICH6 Only
ICH6R / ICH6-M Only
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware action taken on this
value.
Reserved
Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB)
Reserved
Prefetchable (PF) — RO. This bit indicates that this range is not pre-fetchable
Type (TP) — RO. This bit indicates that this range can be mapped anywhere in 32-bit address
space.
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register memory
space.
24h–27h
00000000h
24h
00000000h
2Ch
0000h
No
–
–
27h
2Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Power Well: Core
SATA Controller Registers (D31:F2)
Section
Section
R/WO
16 bits
12.1.15.2.
RO
32 bits
R/W, RO
32 bits
12.3.
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