NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 348

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.1.9
10.1.10
10.1.11
348
HEADTYP—Header Type Register (LPC I/F—D31:F0)
PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Offset Address:
Default Value:
SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only
once after PLTRST# de-assertion.
31:16
15:0
Bit
7:3
2:0
Bit
6:0
Bit
7
Master Latency Count (MLC) — Reserved.
Reserved.
Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration space.
Subsystem ID (SSID) — R/WO. This field is written by BIOS. No hardware action taken on this
value.
Subsystem Vendor ID (SSVID) — R/WO. This field is written by BIOS. No hardware action taken
on this value.
0Dh
00h
0Eh
80h
2C
00000000h
–
2Fh
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
32 bits
RO
8 bits
RO
8 bits
R/WO