NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 263

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

7.1.39
7.1.40
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PLLMC—PLL Miscellaneous Control Register (Mobile Only)
Offset Address:
Default Value:
TCTL—TCO Configuration Register
Offset Address:
Default Value:
31:25
21:0
Bit
Bit
6:3
2:0
24
23
22
7
Reserved
PLL Misc. Control Field 2 — R/W. BIOS shall always program this field as per the BIOS
Specification.
0 = Disable Clock Gating.
1 = Enable Clock Gating..
Reserved
PLL Misc. Control Field 1 — R/W. BIOS shall always program this field as per the BIOS
Specification.
0 = Disable Clock Gating.
1 = Enable Clock Gating..
Reserved
TCO IRQ Enable (IE) — R/W.
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
Reserved
TCO IRQ Select (IS) — R/W. This field specifies on which IRQ the TCO will internally appear. If
not using the APIC, the TCO interrupt must be routed to IRQ9:11, and that interrupt is not
sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC,
the TCO interrupt can also be mapped to IRQ20:23, and can be shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
011 = Reserved
100 = IRQ 20 (only if APIC enabled)
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
When setting the these bits, the IE bit should be cleared to prevent glitching.
When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for
active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC
should be programmed for active-low reception.
2078–207Bh
N/A
3000–3000h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
R/W
32-bit
R/W
8-bit
263