NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 164

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.14.9
5.14.9.1
164
Table 5-33. Transitions Due to Power Button
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled),
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled
PWRBTN# (Power Button)
Event Input Signals and Their Usage
The ICH6 has various input signals that trigger specific events. This section describes those signals
and how they should be used.
The ICH6 PWRBTN# signal operates as a “Fixed Power Button” as described in the Advanced
Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the
input. The state transition descriptions are included in
soon as the PWRBTN# is pressed (but after the debounce logic), and does not depend on when the
Power Button is released.
the Power Button is not a wake event. Refer to Power Button Override Function section below for
further detail.
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine should
unconditionally transition to the G2/S5 state, regardless of present state (S0–S4), even if PWROK
is not active. In this case, the transition to the G2/S5 state should not depend on any particular
response from the processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other
subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.
4-second timer starts counting when the ICH6 is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event.
Once the system has resumed to the S0 state, the 4-second timer starts.
by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it is conceivable that the
user will press and continue to hold the Power Button waiting for the system to awake. Since a
4-second press of the Power Button is already defined as an Unconditional Power down, the power
button timer will be forced to inactive while the power-cycle timer is in progress. Once the
power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4#
Present
S1–S5
S0–S4
S0/Cx
State
G3
PWRBTN# held low for
at least 4 consecutive
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
seconds
Event
Wake Event. Transitions to S0
Unconditional transition to S5
(depending on SCI_EN)
SMI# or SCI generated
Transition/Action
Intel
®
None
state
state
I/O Controller Hub 6 (ICH6) Family Datasheet
Table
5-33. Note that the transitions start as
(e.g., Stop-Grant cycles) or any
No dependence on processor
Software typically initiates a
No effect since no power
Not latched nor detected
Standard wakeup
other subsystem
Sleep state
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