NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 657

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

18.2.10
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
INTCTL—Interrupt Control Register
(Intel
Memory Address: HDBAR + 20h
Default Value:
29:8
Bit
7:0
31
30
®
Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt generation. When set to
1, the Intel High Definition Audio function is enabled to generate an interrupt. This control is in
addition to any bits in the bus specific address space, such as the Interrupt Enable bit in the PCI
configuration space.
NOTE: This bit is not affected by the D3
Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for controller functions.
When set to 1, the controller generates an interrupt when the corresponding status bit gets set due
to a Response Interrupt, a Response Buffer Overrun, and State Change events.
NOTE: This bit is not affected by the D3
Reserved
Stream Interrupt Enable (SIE) — R/W. When set to 1, the individual streams are enabled to
generate an interrupt when the corresponding status bits get set.
A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry being
completed, or as a result of a FIFO error (underrun or overrun) occurring. Control over the
generation of each of these sources is in the associated Stream Descriptor.
The streams are numbered and the SIE bits assigned sequentially, based on their order in the
register set.
Bit 0: input stream 1
Bit 1: input stream 2
Bit 2: input stream 3
Bit 3: input stream 4
Bit 4: output stream 1
Bit 5: output stream 2
Bit 6: output stream 3
Bit 7: output stream 4
High Definition Audio Controller—D27:F0)
00000000h
Intel
®
High Definition Audio Controller Registers (D27:F0)
HOT
HOT
Description
to D0 transition.
to D0 transition.
Attribute:
Size:
R/W
32 bits
657