NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 704

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
19.1.45
19.1.46
19.1.47
704
SMSCS—SMI/SCI Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
VCH—Virtual Channel Capability Header Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
VCAP2—Virtual Channel Capability 2 Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
31:20
19:16
31:24
29:4
15:0
23:0
Bit
Bit
Bit
31
30
3
2
1
0
Power Management SCI Status (PMCS) — R/WC. This bit is set if the Hot-Plug controller needs to
generate an interrupt, and this interrupt has been routed to generate an SCI.
Hot Plug SCI Status (HPCS) — R/WC. This bit is set if the Hot-Plug controller needs to generate an
interrupt, and has this interrupt been routed to generate an SCI.
Reserved
Hot Plug Command Completed SMI Status (HPCCM) — R/WC. This bit is set when SLSTS.CC
(D28:F0/F1/F2/F3:5A, bit 4) transitions from 0 to 1, and MPC.HPME (D28:F0/F1/F2/F3:D8, bit 1) is
set. When this bit is set, an SMI# will be generated.
Hot Plug Attention Button SMI Status (HPABM) — R/WC. This bit is set when SLSTS.ABP
(D28:F0/F1/F2/F3:5A, bit 0) transitions from 0 to 1, and MPC.HPME (D28:F0/F1/F2/F3:D8, bit 1) is
set. When this bit is set, an SMI# will be generated.
Hot Plug Presence Detect SMI Status (HPPDM) — R/WC. This bit is set when SLSTS.PDC
(D28:F0/F1/F2/F3:5A, bit 3) transitions from 0 to 1, and MPC.HPME (D28:F0/F1/F2/F3:D8, bit 1) is
set. When this bit is set, an SMI# will be generated.
Power Management SMI Status (PMMS) — R/WC. This bit is set when RSTS.PS (D28:F0/F1/F2/
F3:60, bit 16) transitions from 0 to ’, and MPC.PMME (D28:F0/F1/F2/F3:D8, bit 1) is set.
Next Capability Offset (NCO) — RO. This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates this is version 1 of the capability structure by the
PCI SIG.
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability item.
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present for VC
arbitration since it is fixed.
Reserved.
DC
00000000h
100
18010002h
108
00000001h
–
–
–
DFh
103h
10Bh
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
32 bits
32 bits
32 bits
R/WC
RO
RO