NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 334

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI-to-PCI Bridge Registers (D30:F0)
9.1.15
9.1.16
9.1.17
9.1.18
334
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
31:0
31:0
15:8
Bit
Bit
Bit
7:0
Bit
7:0
Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field provides the upper 32-bits
of the prefetchable address base.
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field provides the upper 32-bits
of the prefetchable address limit.
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line (vector) the
interrupt is connected to. No hardware action is taken on this register. Since the bridge does not
generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification.
28–2Bh
00000000h
2C–2Fh
00000000h
34h
50h
3C
0000h
–
3Dh
Intel
Description
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
32 bits
R/W
32 bits
RO
16 bits
R/W
8 bits
R/W, RO