NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 9

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
5.20
5.21
5.22
5.19.5 Packet Formats....................................................................................................195
5.19.6 USB Interrupts .....................................................................................................195
5.19.7 USB Power Management ....................................................................................198
5.19.8 USB Legacy Keyboard Operation........................................................................199
USB EHCI Host Controller (D29:F7).................................................................................201
5.20.1 EHC Initialization .................................................................................................201
5.20.2 Data Structures in Main Memory .........................................................................202
5.20.3 USB 2.0 Enhanced Host Controller DMA ............................................................202
5.20.4 Data Encoding and Bit Stuffing ............................................................................202
5.20.5 Packet Formats....................................................................................................202
5.20.6 USB 2.0 Interrupts and Error Conditions .............................................................203
5.20.7 USB 2.0 Power Management ..............................................................................204
5.20.8 Interaction with UHCI Host Controllers ................................................................205
5.20.9 USB 2.0 Legacy Keyboard Operation..................................................................208
5.20.10 USB 2.0 Based Debug Port .................................................................................208
SMBus Controller (D31:F3) ..............................................................................................214
5.21.1 Host Controller .....................................................................................................214
5.21.2 Bus Arbitration .....................................................................................................218
5.21.3 Bus Timing ...........................................................................................................219
5.21.4 Interrupts / SMI# ..................................................................................................220
5.21.5 SMBALERT# .......................................................................................................221
5.21.6 SMBus CRC Generation and Checking...............................................................221
5.21.7 SMBus Slave Interface ........................................................................................221
AC ’97 Controller (Audio D30:F2, Modem D30:F3) ..........................................................226
5.22.1 PCI Power Management......................................................................................228
5.22.2 AC-Link Overview ................................................................................................228
5.19.4.5 Frame Number Field ............................................................................195
5.19.4.6 Data Field.............................................................................................195
5.19.4.7 Cyclic Redundancy Check (CRC) ........................................................195
5.19.6.1 Transaction-Based Interrupts...............................................................196
5.19.6.2 Non-Transaction Based Interrupts .......................................................198
5.20.1.1 BIOS Initialization.................................................................................201
5.20.1.2 Driver Initialization................................................................................201
5.20.1.3 EHC Resets .........................................................................................202
5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads ........................................203
5.20.7.1 Pause Feature .....................................................................................204
5.20.7.2 Suspend Feature .................................................................................204
5.20.7.3 ACPI Device States .............................................................................204
5.20.7.4 ACPI System States ............................................................................205
5.20.7.5 Mobile Considerations .........................................................................205
5.20.8.1 Port-Routing Logic ...............................................................................206
5.20.8.2 Device Connects ..................................................................................207
5.20.8.3 Device Disconnects .............................................................................207
5.20.8.4 Effect of Resets on Port-Routing Logic ................................................208
5.20.10.1 Theory of Operation ............................................................................209
5.21.1.1 Command Protocols ............................................................................215
5.21.3.1 Clock Stretching ...................................................................................219
5.21.3.2 Bus Time Out (Intel
5.21.7.1 Format of Slave Write Cycle ................................................................222
5.21.7.2 Format of Read Command ..................................................................223
5.21.7.3 Format of Host Notify Command .........................................................225
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ICH6 as SMBus Master) ....................................219
Contents
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