NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 331

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

9.1.10
9.1.11
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
This timer controls the amount of time the ICH6 PCI-to-PCI bridge will burst data on its secondary
interface. The counter starts counting down from the assertion of FRAME#. If the grant is
removed, then the expiration of this counter will result in the de-assertion of FRAME#. If the grant
has not been removed, then the ICH6 PCI-to-PCI bridge may continue ownership of the bus.
IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
15:12
11:8
Bit
7:3
2:0
Bit
7:4
3:0
Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of PCI clocks, in
8-clock increments, that the ICH6 remains as master of the bus.
Reserved
I/O Limit Address Limit bits [15:12] — R/W. I/O These base address bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
II/O Limit Address Capability (IOLC) — RO. This field indicates that the bridge does not support 32-
bit I/O addressing.
I/O Base Address (IOBA) — R/W. These I/O Base address bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Base Address Capability (IOBC) — RO. This field indicates that the bridge does not support 32-
bit I/O addressing.
1Bh
00h
1C-1Dh
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
R/W, RO
8 bits
R/W, RO
16 bits
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