NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 249

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

7.1.1
7.1.2
Intel
Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
VCH—Virtual Channel Capability Header Register
Offset Address:
Default Value:
VCAP1—Virtual Channel Capability #1 Register
Offset Address:
Default Value:
341C–341Fh
3E08–3E09h
3E48–3E49h
31:20
19:16
31:12
11:10
15:0
Bit
Bit
9:8
6:4
3:0
3E0Eh
3E4Eh
Offset
7
Next Capability Offset (NCO) — RO. This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates support as a version 1 capability structure.
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability item.
Reserved
Port Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the port arbitration
table is 4 bits (to allow up to 8 ports).
Reference Clock (RC) — RO. Fixed at 100 ns.
Reserved
Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there are no additional
VCs of low priority with extended capabilities.
Reserved
Mnemonic
CSIR1
CSIR3
CSIR2
CSIR4
CG
0000–0003h
10010002h
0004–0007h
00000801h
Clock Gating
Chipset Initialization Register 1
Chipset Initialization Register 4
Chipset Initialization Register 2
Chipset Initialization Register 4
Register Name
Description
Description
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
00000000h
RO
32-bit
RO
32-bit
Default
0000h
0000h
00h
00h
R/W, RO
Type
R/W
R/W
R/W
R/W
249