NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 573

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

15.2.3
15.2.4
15.2.5
15.2.6
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
HST_CMD—Host Command Register (SMBus—D31:F3)
Register Offset:
Default Value:
XMIT_SLVA—Transmit Slave Address Register
(SMBus—D31:F3)
Register Offset:
Default Value:
This register is transmitted by the host controller in the slave address field of the SMBus protocol.
HST_D0—Host Data 0 Register (SMBus—D31:F3)
Register Offset:
Default Value:
HST_D1—Host Data 1 Register (SMBus—D31:F3)
Register Offset:
Default Value:
Bit
7:1
Bit
7:0
Bit
7:0
Bit
7:0
0
Address — R/W. This field provides a 7-bit address of the targeted slave.
RW — R/W. Direction of the host transfer.
0 = Write
1 = Read
Data0/Count — R/W. This field contains the 8-bit data sent in the DATA0 field of the SMBus
protocol. For block write commands, this register reflects the number of bytes to transfer. This
register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a
count above 32 will result in unpredictable behavior. The host controller does not check or log illegal
block counts.
Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol during the
execution of any command.
This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol
during the execution of any command.
SMBASE + 03h
00h
SMBASE + 04h
00h
SMBASE + 05h
00h
SMBASE + 06h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
R/W
8 bits
R/W
8 bits
R/W
8 bits
R/W
8 bits
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