NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 496

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.3.2.6
496
PxIE—Port [3:0] Interrupt Enable Register (D31:F2)
Address Offset:
Default Value:
This register enables and disables the reporting of the corresponding interrupt to system software.
When a bit is set (‘1’) and the corresponding interrupt condition is active, then an interrupt is
generated. Interrupt sources that are disabled (‘0’) are still reflected in the status registers.
21:8
Bit
31
30
29
28
27
26
25
24
23
22
7
6
5
4
3
2
1
0
Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect not supported.
Task File Error Enable (TFEE) — R/W . When set, and GHC.IE and PxTFD.STS.ERR (due to a
reception of the error register from a received FIS) are set, the Intel
Host Bus Fatal Error Enable (HBFE) — R/W . When set, and GHC.IE and PxS.HBFS are set, the
ICH6 will generate an interrupt.
Host Bus Data Error Enable (HBDE) — R/W . When set, and GHC.IE and PxS.HBDS are set, the
ICH6 will generate an interrupt.
Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and PxIS.HBDS is set, the
ICH6 will generate an interrupt.
Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and PxIS.INFS is set,
the ICH6 will generate an interrupt.
Reserved - Should be written as 0
Overflow Error Enable (OFE) — R/W . When set, and GHC.IE and PxS.OFS are set, the ICH6 will
generate an interrupt.
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and PxIS.IPMS are set,
the ICH6 will generate an interrupt.
NOTE: Should be written as 0. Port Multiplier not supported by ICH6.
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and PxIS.PRCS
is set, the ICH6 shall generate an interrupt.
Reserved - Should be written as 0
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH6 will generate an
interrupt.
For systems that do not support an interlock switch, this bit shall be a read-only 0.
Port Change Interrupt Enable (PCE) — R/W . When set, and GHC.IE and PxS.PCS are set, the
ICH6 will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE) — R/W . When set, and GHC.IE and PxS.DPS are
set, the ICH6 will generate an interrupt
Unknown FIS Interrupt Enable (UFIE) — R/W . When set, and GHC.IE is set and an unknown FIS
is received, the ICH6 will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SDBE) — R/W . When set, and GHC.IE and PxS.SDBS are
set, the ICH6 will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE) — R/W . When set, and GHC.IE and PxS.DSS are set, the
ICH6 will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE) — R/W . When set, and GHC.IE and PxS.PSS are set, the
ICH6 will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE) — R/W . When set, and GHC.IE and
PxS.DHRS are set, the ICH6 will generate an interrupt.
Port 0: ABAR + 114h
Port 1: ABAR + 194h (Desktop Only)
Port 2: ABAR + 214h
Port 3: ABAR + 294h (Desktop Only)
00000000h
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W, RO
32 bits
®
ICH6 will generate an interrupt.