NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 565

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

15.1.4
15.1.5
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register (SMBus—D31:F3)
Address:
Default Value:
effect.
RID—Revision Identification Register (SMBus—D31:F3)
Offset Address:
Default Value:
10:9
Bit
2:0
Bit
7:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Parity error detected.
Signaled System Error (SSE) — R/WC.
0 = No system error detected.
1 = System error detected.
Received Master Abort (RMA) — RO. Hardwired to 0.
Received Target Abort (RTA) — RO. Hardwired to 0.
Signaled Target Abort (STA) — R/WC.
0 = ICH6 did Not terminate transaction for this function with a target abort.
1 = The function is targeted with a transaction that the Intel
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL# assertion for
positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list structures in
this function
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from
the state of the Interrupt Enable bit in the PCI Command register.
Reserved
Revision ID — RO. Refer to the Intel
the value of the Revision ID Register
06
0280h
08h
See bit description
–
07h
®
I/O Controller Hub 6 (ICH6) Family Specification Update for
Attributes:RO, R/WC
Size: 16 bits
Description
Description
Attribute:
Size:
SMBus Controller Registers (D31:F3)
®
ICH6 terminates with a target abort.
8 bits
RO
565