NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 680

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
19.1.4
680
PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when the root port receives a command or data from the backbone with a parity error. This
Signaled System Error (SSE) — R/WC.
0 = No system error signaled.
1 = Set when the root port signals a system error to the internal SERR# logic.
Received Master Abort (RMA) — R/WC.
0 = Root port has not received a completion with unsupported request status from the backbone.
1 = Set when the root port receives a completion with unsupported request status from the
Received Target Abort (RTA) — R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
1 = Set when the root port receives a completion with completer abort from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = No target abort received.
1 = Set whenever the root port forwards a target abort received from the downstream device onto
DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base Specification .
Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error received.
1 = Set when the root port receives a completion with a data parity error on the backbone and
Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base Specification .
Reserved
66 MHz Capable — Reserved per the PCI Express* Base Specification .
Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status — RO. Indicates status of Hot-Plug and power management interrupts on the root
port that result in INTx# message generation.
0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of
PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3:04h:bit 10).
Reserved
is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
backbone.
the backbone.
PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.
06
0010h
–
07h
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
16 bits
R/WC, RO