NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 429

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.9.9
10.9.10
10.9.11
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
TCO_WDCNT—TCO Watchdog Control Register
Offset Address:
Default Value:
Power Well:
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address:
Default Value:
Power Well:
TCO_TMR—TCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
15:10
Bit
7:2
Bit
9:0
Bit
7:0
1
0
Reserved
IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by
the ICH6’s SERIRQ logic. This bit must be a 1 (default) if the ICH6 is expected to receive IRQ12
assertions from a SERIRQ device.
IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by
the ICH6’s SERIRQ logic. This bit must be a 1 (default) if the ICH6 is expected to receive IRQ1
assertions from a SERIRQ device.
Reserved
TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the TCO_RLD register
is written. Values of 0000h or 0001h will be ignored and should not be attempted. The timer is
clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to
613.8 seconds. Note: The timer has an error of ± 1 tick (0.6s).
The TCO Timer will only count down in the S0 state.
On LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
Watchdog Status (WDSTATUS) — R/W. The value written to this register will be sent in the Alert
TCOBASE + 0Eh
00h
Resume
TCOBASE + 10h
11h
Core
TCOBASE +12h
0004h
No
Description
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Power Well:
R/W
8 bits
R/W
8 bits
R/W
16-bit
Core
429