NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 568

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
15.1.14
568
HOSTC—Host Configuration Register (SMBus—D31:F3)
Address Offset:
Default Value:
7:3
Bit
2
1
0
Reserved
I
0 = SMBus behavior.
1 = The ICH6 is enabled to communicate with I
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit
2
C_EN — R/W.
commands.
Section 5.21.4
This bit needs to be set for SMBALERT# to be enabled.
(offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host controller to interrupt or
SMI#. Note that the SMB Host controller will not respond to any new requests until all interrupt
requests have been cleared.
40h
00h
(Interrupts / SMI#).
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
2
C devices. This will change the formatting of some
R/W
8 bits