NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 693

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

19.1.28
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
LCTL—Link Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
15:8
Bit
1:0
7
6
5
4
3
2
Reserved
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to
Common Clock Configuration (CCC) — R/W.
0 = The ICH6 and device are not using a common reference clock.
1 = The ICH6 and device are operating with a distributed common reference clock.
Retrain Link (RL) — WO.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3:52, bit 11) to check the status of training.
Link Disable (LD) — R/W.
0 = Link enabled.
1 = The root port will disable the link.
Read Completion Boundary Control (RCBC) — RO. This bit indicates the read completion
boundary is 64 bytes.
Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether the root port should
enter L0s or L1 or both.
entering L0.
Bits
00b
01b
10b
11b
50–51h
0000h
Disabled
L0s Entry is Enabled
L1 Entry is Enabled
L0s and L1 Entry Enabled
Definition
Description
Attribute:
Size:
PCI Express* Configuration Registers
R/W, WO, RO
16 bits
693