NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 547

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

14.2.2
Intel
Table 14-3. Enhanced Host Controller Operational Register Address Map
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: Software must read and write these registers using only DWord accesses.These registers are
Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers are located
after the capabilities registers. The operational register base must be DWord-aligned and is
calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address
of the enhanced host controller register address space (MEM_BASE). Since CAPLENGTH is
always 20h,
divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are implemented in the core
power well. Unless otherwise noted, the core well registers are reset by the assertion of any of the
following:
MEM_BASE
•
•
•
B4–3FFh
+ Offset
2C–2Fh
3C–5Fh
6C–6Fh
7C–7Fh
A0–B3h
20–23h
24–27h
28–2Bh
30–33h
34–37h
38–3Bh
60–63h
64–67h
68–6Bh
70–73h
74–77h
78–7Bh
80–83h
84–9Fh
Core well hardware reset
HCRESET
D3-to-D0 reset
Table 14-3
CONFIGGLAG
USB2.0_CMD
USB2.0_INTR
USB2.0_STS
CLISTBASE
ASYNCLIS-
Mnemonic
SEGMENT
PORT0SC
PORT1SC
PORT2SC
PORT3SC
PORT4SC
PORT5SC
PORT6SC
PORT7SC
FRINDEX
CTRLDS-
PERODI-
TADDR
—
—
—
—
already accounts for this offset. All registers are 32 bits in length.
USB 2.0 Command
USB 2.0 Status
USB 2.0 Interrupt Enable
USB 2.0 Frame Index
Control Data Structure Segment
Period Frame List Base Address
Current Asynchronous List
Address
Reserved
Configure Flag
Port 0 Status and Control
Port 1 Status and Control
Port 2 Status and Control
Port 3 Status and Control
Port 4 Status and Control
Port 5 Status and Control
Port 6 Status and Control
Port 7 Status and Control
Reserved
Debug Port Registers
Reserved
Register Name
EHCI Controller Registers (D29:F7)
00080000h
00001000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
Undefined
Undefined
Undefined
Default
0h
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Special
Notes
See register
description
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
Type
R/W,
R/W,
R/W,
R/W,
R/W,
R/W,
R/W,
R/W,
R/W,
R/W
R/W
R/W
R/W
RO
RO
RO
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