NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 664

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.2.25
18.2.26
664
®
High Definition Audio Controller Registers (D27:F0)
RIRBCTL—RIRB Control Register
(Intel
Memory Address: HDBAR + 5Ch
Default Value:
RIRBSTS—RIRB Status Register
(Intel
Memory Address: HDBAR + 5Dh
Default Value:
Bit
7:3
Bit
7:3
2
1
0
2
1
0
®
®
Reserved.
Response Overrun Interrupt Control — R/W. If this bit is set, the hardware will generate an
interrupt when the Response Overrun Interrupt Status bit (HDBAR + 5Dh: bit 2) is set.
Enable RIRB DMA Engine — R/W.
0 = DMA stop
1 = DMA run
After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will
physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from
this bit to verify that the DMA engine is truly stopped.
Response Interrupt Control — R/W.
0 = Disable Interrupt
1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR when an
Reserved.
Response Overrun Interrupt Status — R/WC. Software sets this bit to 1 when the RIRB DMA
engine is not able to write the incoming responses to memory before additional incoming responses
overrun the internal FIFO. When the overrun occurs, the hardware will drop the responses which
overrun the buffer. An interrupt may be generated if the Response Overrun Interrupt Control bit is
set. Note that this status bit is set even if an interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
Reserved.
Response Interrupt — R/WC. Hardware sets this bit to 1 when an interrupt has been generated
after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is
encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit is set even if an
interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). The N counter
is reset when the interrupt is generated.
00h
00h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/WC
8 bits