NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 608

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

AC ’97 Modem Controller Registers (D30:F3)
17.1.1
17.1.2
17.1.3
608
VID—Vendor Identification Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
DID—Device Identification Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
PCICMD—PCI Command Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification for complete details
on each bit.
15:11
15:0
15:0
Bit
Bit
Bit
10
9
8
7
6
5
4
3
2
1
0
Vendor ID.
Device ID.
Reserved. Read 0.
Interrupt Disable (ID) — R/W.
0 = The INTx# signals may be asserted and MSIs may be generated.
1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate MSIs.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. This bit controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — RO. Hardwired to 0, AC ‘97 does not respond to memory
accesses.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable access. (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
00
8086
No
02
266Dh
No
04
0000h
No
–
–
–
01h
03h
05h
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
RO
Core
RO
Core
16 bits
Core
16 Bits
16 Bits
R/W, RO