NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 494

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.3.2.4
12.3.2.5
494
PxIS—Port [3:0] Interrupt Status Register (D31:F2)
PxFBU—Port [3:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset:
Default Value:
Address Offset:
Default Value:
31:3
21:8
Bit
2:0
Bit
31
30
29
28
27
26
25
24
23
22
Command List Base Address Upper (CLBU) — R/W . This field indicates the upper 32-bits for the
received FIS base for this port.
Note that these bits are not reset on a HBA reset.
Reserved
Cold Port Detect Status (CPDS) — RO . Cold presence not supported.
Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is updated by
the device and the error bit (PxTFD.bit 0) is set.
Host Bus Fatal Error Status (HBFS) — R/WC . This bit indicates that the Intel
an error that it cannot recover from due to a bad software pointer. In PCI, such an indication would
be a target or master abort.
Host Bus Data Error Status (HBDS) — R/WC . Indicates that the ICH6 encountered a data error
(uncorrectable ECC / parity) when reading from or writing to system memory.
Interface Fatal Error Status (IFS) — R/WC . Indicates that the ICH6 encountered an error on the
SATA interface which caused the transfer to stop.
Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the ICH6 encountered an error on
the SATA interface but was able to continue operation.
Reserved
Overflow Status (OFS) — R/WC . Indicates that the ICH6 received more bytes from a device than
was specified in the PRD table for the command.
Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH6 received a FIS from a
device whose Port Multiplier field did not match what was expected.
NOTE: Port Multiplier not supported by ICH6.
PhyRdy Change Status (PRCS) — RO. When set to 1 indicates the internal PhyRdy signal
changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the
register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared.
Note that the internal PhyRdy signal also transitions when the port interface enters partial or slumber
power management states. Partial and slumber must be disabled when Surprise Removal
Notification is desired, otherwise the power management state transitions will appear as false
insertion and removal events.
Reserved
Port 0: ABAR + 10Ch
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch
Port 3: ABAR + 28Ch
Undefined
Port 0: ABAR + 110h
Port 1: ABAR + 190h (Desktop Only)
Port 2: ABAR + 210h
Port 3: ABAR + 290h (Desktop Only)
00000000h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
R/WC, RO
32 bits
32 bits
R/W
®
ICH6 encountered