NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 435

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.10.7
10.10.8
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]
Offset Address:
Default Value:
Lockable:
GP_IO_SEL2—GPIO Input/Output Select 2 Register[63:32]
Offset Address:
Default Value:
Lockable:
17, 9:8
31:18
17:16
15:10
Bit
Bit
9:8
7:3
2:0
GPIO_USE_SEL2[49, 41:40] — R/W. Each bit in this register enables the corresponding GPIO (if it
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as
a GPIO rather than as their native function. After just a PLTRST#, the GPIO in the core well are
configured as GPIO.
NOTES:
Always 0. No corresponding GPIO.
Always 0. Outputs.
Always 0. No corresponding GPIO.
Always 0. Inputs.
Always 0. No corresponding GPIO.
GP_IO_SEL2[34:32] — R/W.
0 = GPIO signal is programmed as an output.
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is programmed as an
1. The following bits are not implemented because there is no corresponding GPIO: 3:7, 10:15,
2. The following bits are always 1 because they are unmultiplexed: 1:2
3. Bit 16 is not implemented because the GPIO selection will be controlled by Bit 8 (REQ/GNT pair)
4. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have no
5. The following bits are not implemented because they are determined by the Desktop/Mobile
18:31.
effect.
configuration: 0
input.
GPIOBASE +30h
00000006h
No
GPIOBASE +34h
00000300h
No
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
for 16:0
R/W
32-bit
Processor I/O for 17, Core
R/W
32-bit
Core
435