NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 189

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.17.4.2
5.17.4.2.1
5.17.4.2.2
5.17.4.2.3
Intel
Figure 5-8. SATA Power States
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Power State Transitions
Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would be most
analogous to PCI CLKRUN# (in power savings, not in mechanism), where the interface can have
power saved while no commands are pending. The SATA controller defines PHY layer power
management (as performed via primitives) as a driver operation from the host side, and a device
proprietary mechanism on the device side. The SATA controller accepts device transition types, but
does not issue any transitions as a host. All received requests from a SATA device will be ACKed.
When an operation is performed to the SATA controller such that it needs to use the SATA cable,
the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a
COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same
action.
Device D1, D3 States
These states are entered after some period of time when software has determined that no
commands will be sent to this device for some time. The mechanism for putting a device in these
states does not involve any work on the host controller, other then sending commands over the
interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY
IMMEDIATE” command.
Host Controller D3
After the interface and device have been put into a low power state, the SATA host controller may
be put into a low power state. This is performed via the PCI power management registers in
configuration space. There are two very important aspects to note when using PCI power
management.
•
•
When the power state is D3, only accesses to configuration space are allowed. Any attempt to
access the memory or I/O spaces will result in master abort.
When the power state is D3, no interrupts may be generated, even if they are enabled. If an
interrupt status bit is pending when the controller transitions to D0, an interrupt may be
generated.
PHY =
Ready
HOT
Partial
PHY =
Device = D0
State
Slumber
PHY =
Intel
®
Resume Latency
ICH6 SATA Controller = D0
disabled)
Off (port
PHY =
Power
Slumber
PHY =
Device = D1
disabled)
Off (port
PHY =
Slumber
PHY =
Functional Description
Device = D3
disabled)
Off (port
PHY =
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