NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 346

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.1.4
346
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
effect.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity error on the
internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0
0 = Parity Error Not detected.
1 = Parity Error detected.
Signaled System Error (SSE) — R/WC. Set when the LPC bridge signals a system error to the
internal SERR# logic.
Master Abort Status (RMA) — R/WC.
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the backbone.
Received Target Abort (RTA) — R/WC.
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the backbone.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal backbone.
Reserved.
66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal backbone.
Capabilities List (CLIST) — RO. No capability list exist on the LPC bridge.
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
Reserved.
• LPC bridge receives a completion packet from the backbone from a previous request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
06
0200h
No
–
07h
Intel
®
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
RO, R/WC
Core
16-bit