NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 329

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

9.1.5
9.1.6
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
23:16
10:9
15:8
Bit
7:0
Bit
7:5
2:0
Bit
7:0
13
12
11
8
4
3
0
Revision ID — RO. Refer to the Intel
the value of the Revision ID Register
Received Master Abort (RMA) — R/WC.
0 = No master abort received.
1 = Set when the bridge receives a master abort status from the backbone.
Received Target Abort (RTA) — R/WC.
0 = No target abort received.
1 = Set when the bridge receives a target abort status from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the backbone.
Reserved.
Data Parity Error Detected (DPD) — R/WC.
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a previous request,
Reserved.
Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate interrupts.
Reserved
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI.
0 = Disable
0 = Enable
Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge.
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractive decode
and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6).
08h
See bit description
09-0Bh
060401h
®
I/O Controller Hub 6 (ICH6) Family Specification Update for
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
8 bits
RO
RO
32 bits
329