NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 534

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.1.16
14.1.17
534
NXT_PTR1—Next Item Pointer #1 Register
PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Bit
7:0
Bit
7:0
Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power
Management capabilities field.
Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which indicates that the
next capability registers begin at configuration offset 58h. This register is writable when the
WRT_RDONLY bit (D29:F7:80h, bit 0) is set. This allows BIOS to effectively hide the Debug Port
capability registers, if necessary. This register should only be written during system initialization
before the plug-and-play software has enabled any master-initiated traffic. Only values of 58h
(Debug Port visible) and 00h (Debug Port invisible) are expected to be programmed in this register.
NOTE: Register not reset by D3-to-D0 warm reset.
50h
01h
51h
58h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W (special)
8 bits