NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 590

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2)
16.1.18
16.1.19
16.1.20
590
INT_PN—Interrupt Pin Register (Audio—D30:F2)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt pin is used for the AC '97 module interrupt. The AC '97
interrupt is internally OR’d to the interrupt controller with the PIRQB# signal.
PCID—Programmable Codec Identification Register
(Audio—D30:F2)
Address Offset:
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This
register is not affected by the D3
only before any AC ’97 codec accesses.
CFG—Configuration Register (Audio—D30:F2)
Address Offset:
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This
register is not affected by the D3
Bit
7:0
Bit
7:4
3:2
1:0
Bit
7:1
0
AC '97 Interrupt Routing — RO. This reflects the value of D30IP.AAIP in chipset configuration space.
Reserved.
Tertiary Codec ID (TID ) — R/W. These bits define the encoded ID that is used to address the
tertiary codec I/O space. Bit 1 is the first bit sent and Bit 0 is the second bit sent on ACZ_SDOUT
during slot 0.
Secondary Codec ID (SCID) — R/W. These two bits define the encoded ID that is used to address
the secondary codec I/O space. The two bits are the ID that will be placed on slot 0, bits 0 and 1,
upon an I/O access to the secondary codec. Bit 1 is the first bit sent and bit 0 is the second bit sent
on ACZ_SDOUT during slot 0.
Reserved—RO.
I/O Space Enable (IOSE) — R/W.
0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h become read
1 = Enable.
only registers. Additionally, bit 0 of the I/O BARs at offsets 10h and 14h are hardwired to 0 when
this bit is 0. This is the default state for the I/O BARs. BIOS must explicitly set this bit to allow a
legacy driver to work.
3Dh
See Description
No
40h
09h
No
41h
00h
No
HOT
HOT
to D0 transition. The value in this register must be modified
to D0 transition.
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
RO
Core
Core
Core
8 bits
R/W
8 bits
R/W
8 bits