NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 198

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.19.6.2
5.19.7
198
Table 5-43. Bits Maintained in Low Power States
Non-Transaction Based Interrupts
If an ICH6 process error or system error occur, the ICH6 halts and immediately issues a hardware
interrupt to the system.
Resume Received
This event indicates that the ICH6 received a RESUME signal from a device on the USB bus
during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware
interrupt is signaled to the system allowing the USB to be brought out of the suspend state and
returned to normal operation.
ICH6 Process Error
The HC monitors certain critical fields during operation to ensure that it does not process corrupted
data structures. These include checking for a valid PID and verifying that the MaxLength field is
less than 1280. If it detects a condition that would indicate that it is processing corrupted data
structures, it immediately halts processing, sets the HC Process Error bit in the HC Status register
and signals a hardware interrupt to the system.
This interrupt cannot be disabled through the Interrupt Enable register.
Host System Error
The ICH6 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occur. When this
error occurs, the ICH6 clears the Run/Stop bit in the Command register to prevent further
execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable
register.
USB Power Management
The Host controller can be put into a suspended state and its power can be removed. This requires
that certain bits of information are retained in the resume power plane of the ICH6 so that a device
on a port may wake the system. Such a device may be a fax-modem, which will wake up the
machine to receive a fax or take a voice message. The settings of the following bits in I/O space
will be maintained when the ICH6 enters the S3, S4, or S5 states.
When the ICH6 detects a resume event on any of its ports, it sets the corresponding USB_STS bit
in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI
generated.
Port Status and Control
Command
Register
Status
10h & 12h
Offset
00h
02h
Bit
12
3
2
2
6
8
Intel
Enter Global Suspend Mode (EGSM)
Resume Detect
Port Enabled/Disabled
Resume Detect
Low-speed Device Attached
Suspend
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Description