NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 121

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.6
Intel
Figure 5-4. Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the ICH6 that supports two LPC bus
masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ0#)
and 0011 for grants to bus master #1 (requested via LDRQ1#.). Thus, no registers are needed to
configure the START fields for a particular bus master.
DMA Operation (D31:F0)
The ICH6 supports LPC DMA using the ICH6’s DMA controller. The DMA controller has
registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using
registers in the PCI configuration space. These registers allow configuration of the channels for use
by LPC DMA.
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven
independently programmable channels
DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to channels 5–7. DMA channel 4
is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode
(DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests
from DMA slaves, the DMA controller also responds to requests that software initiates. Software
may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0]
are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit,
count-by-words (address shifted) transfers.
ICH6 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each
channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant
bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most
significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization following a
DMA termination.
®
ICH6 DMA Controller
Channel 1
Channel 2
Channel 3
Channel 0
DMA-1
(Figure
5-4). DMA controller 1 (DMA-1) corresponds to
Channel 4
Channel 5
Channel 6
Channel 7
DMA-2
Functional Description
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