NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 504

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.3.2.13
504
PxSACT—Port [3:0] Serial ATA Active (D31:F2)
Address Offset:
Default Value:
15:0
31:0
Bit
Bit
Error (ERR) — R/WC . The ERR field contains error information for use by host software in
determining the appropriate response to the error condition.
If one or more of bits 11:8 of this register are set, the controller will stop the current transfer.
Bits
15:12 Reserved
11
10
9
8
7:2
1
0
Device Status (DS) — R/W . System software sets this bit for SATA queuing operations prior to
setting the PxCI.CI bit in the same command slot entry. This field is cleared via the Set Device Bits
FIS.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by
software, and as a result of a COMRESET or SRST.
Description
Internal Error (E) : The SATA controller failed due to a master or target abort when
Protocol Error (P) : A violation of the Serial ATA protocol was detected. Note: The ICH6
Persistent Communication or Data Integrity Error (C) : A communication error that was
Transient Data Integrity Error (T) : A data integrity error occurred that was not recovered
Reserved
Recovered Communications Error (M) : Communications between the device and host
Recovered Data Integrity Error (I) : A data integrity error occurred that was recovered by
attempting to access system memory.
does not set this bit for all protocol violations that may occur on the SATA link.
not recovered occurred that is expected to be persistent. Persistent communications
errors may arise from faulty interconnect with the device, from a device that has been
removed or has failed, or a number of other causes.
by the interface.
was temporarily lost but was re-established. This can arise from a device temporarily
being removed, from a temporary loss of Phy synchronization, or from other causes and
may be derived from the PhyNRdy signal between the Phy and Link layers.
the interface through a retry operation or other recovery action.
Port 0: ABAR + 134h
Port 1: ABAR + 1B4h (Desktop Only)
Port 2: ABAR + 234h
Port 3: ABAR + 2B4h (Desktop Only)
00000000h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W
32 bits