NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 692

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
19.1.27
692
LCAP—Link Capabilities Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
31:24
23:18
17:15
14:12
11:10
9:4
3:0
Bit
Port Number (PN) — RO. This field indicates the port number for the root port. This value is
different for each implemented port:
Reserved
L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs.
L0s Exit Latency (EL0) — RO. This field indicates as exit latency based upon common-clock
configuration.
NOTE: LCLT.CCC is at D28:F0/F1/F2/F3:50h:bit 6
Active State Link PM Support (APMS) — R/WO. This field indicates what level of active state link
power management is supported on the root port. Value fixed at 11b.
Maximum Link Width (MLW) — RO. For the root ports, several values can be taken, based upon
the value of the chipset configuration register field RPC.PC (Chipset Configuration Registers:Offset
0224h:bits1:0):
Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.
LCLT.CCC
Function
Port #
D28:F0
D28:F1
D28:F2
D28:F3
0
1
Bits
00b
01b
10b
11b
1
2
3
4
4C
See bit description
–
4Fh
Value of MLW Field
MPC.UCEL (D28:F0/F1/F2/F3:D8h:bits20:18)
MPC.CCEL (D28:F0/F1/F2/F3:D8h:bits17:15)
Neither L0s nor L1 are supported
L0s Entry Supported
L1 Entry Supported
Both L0s and L1 Entry Supported
RPC.PC=00b
Port #
1
2
3
4
01h
01h
01h
01h
Value of EL0 (these bits)
Definition
PN Field
Value of
01h
02h
03h
04h
RPC.PC=11b
Intel
04h
01h
01h
01h
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
32 bits
R/W, RO