NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 554

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.2.2.5
14.2.2.6
554
PERIODICLISTBASE—Periodic Frame List Base Address
CTRLDSSEGMENT—Control Data Structure Segment
Register
Offset:
Default Value:
This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data
structures. Since the ICH6 hardwires the 64-bit Addressing Capability field in HCCPARAMS to 1,
then this register is used with the link pointers to construct 64-bit addresses to EHCI control data
structures. This register is concatenated with the link pointer from either the
PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a
64-bit address. This register allows the host software to locate all control data structures within the
same 4 GB memory segment.
Register
Offset:
Default Value:
This 32-bit register contains the beginning address of the Periodic Frame List in the system
memory. Since the ICH6 host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit
Addressing Capability field in the HCCSPARAMS register) (offset 08h, bit 0), then the most
significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT
register. HCD loads this register prior to starting the schedule execution by the host controller. The
memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned.
The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the
Host controller to step through the Periodic Frame List in sequence.
31:12
31:12
11:0
11:0
Bit
Bit
Upper Address[63:44] — RO. Hardwired to 0s. The ICH6 EHC is only capable of generating
addresses up to 16 terabytes (44 bits of address).
Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when forming a
control data structure address.
Base Address (Low) — R/W. These bits correspond to memory address signals [31:12],
respectively.
Reserved. Must be written as 0’s. During runtime, the value of these bits are undefined.
MEM_BASE + 30–33h
00000000h
MEM_BASE + 34–37h
00000000h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W, RO
32 bits