NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 171

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.14.11.2
5.14.11.3
5.14.11.4
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5.14.11.6
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion Stretch
Note:
SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal
should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4#
logic in the ICH6 provides a mechanism to fully cycle the power to the DRAM and/or detect if the
power is not cycled for a minimum time.
Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4# signal.
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid. PWROK
should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached their nominal
values.
CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is internally
AND’d with the PWROK signal that comes from the system power supply.
VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the regulator are
on and within specification. VRMPWRGD may go active before or after the PWROK from the
main power supply. ICH6 has no dependency on the order in which these two signals go active or
inactive.
BATLOW# (Battery Low) (Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not sufficient power.
It also causes an SMI# if the system is already in an S0 state.
1. SYSRESET# is recommended for implementing the system reset button. This saves external
2. If the PWROK input is used to implement the system reset button, the ICH6 does not provide
3. If a design has an active-low reset button electrically AND’d with the PWROK signal from the
4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less
5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.
logic that is needed if the PWROK input is used. Additionally, it allows for better handling of
the SMBus and processor resets, and avoids improperly reporting power failures.
any mechanism to limit the amount of time that the processor is held in reset. The platform
must externally guarantee that maximum reset assertion specs are met.
power supply and the processor’s voltage regulator module the ICH6 PWROK_FLR bit will
be set. The ICH6 treats this internally as if the RSMRST# signal had gone active. However, it
is not treated as a full power failure. If PWROK goes inactive and then active (but RSMRST#
stays high), then the ICH6 reboots (regardless of the state of the AFTERG3 bit). If the
RSMRST# signal also goes low before PWROK goes high, then this is a full power failure,
and the reboot policy is controlled by the AFTERG3 bit.
than one RTC clock period may not be detected by the ICH6.
Functional Description
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