NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 415

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Bit
8
7
6
5
4
3
2
1
0
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not affected by a
hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved
TCOSCI_EN — R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN — R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
NOTE: This bit is also used for Intel High Definition Audio when the Intel High Definition Audio
USB2_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
HOT_PLUG_EN — R/W.
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1 = Enables the ICH6 to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow
THRM_EN — R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
the PCI Express ports to cause an SCI due to hot-plug events.
THRM_STS bit and generate a power management event (SCI or SMI).
host controller is enabled rather than the AC97 host controller.
Description
LPC Interface Bridge Registers (D31:F0)
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