NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 337
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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9.1.21
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PDPR—PCI Decode Policy Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
Bit
7:1
0
Reserved
Subtractive Decode Policy (SDP) — R/W.
0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other
1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the corresponding
NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.
device on the backbone (primary interface) to the PCI bus (secondary interface).
Space Enable bit is set in the Command register.
42h
00h
Description
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
R/W
8 bits
337
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