NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 396

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
396
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
Bit
2
1
0
period may not be detected by the ICH6.
Minimum SLP_S4# Assertion Width Violation Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before
CPU Power Failure (CPUPWR_FLR) — R/WC.
0 = Software (typically BIOS) clears this bit by writing a 0 to it.
1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while the system
PWROK Failure (PWROK_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3 state.
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1 state. The bit
NOTE: See
NOTE: In the case of true PWROK failure, PWROK will go low first before the VRMPWRGD.
the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). The ICH6 begins the
timer when SLP_S4# is asserted during S4/S5 entry, or when the RSMRST# input is de-
asserted during G3 exit. Note that this bit is functional regardless of the value in the SLP_S4#
Assertion Stretch Enable (D31:F0:Offset A4h:bit 3).
was in an S0 or S1 state.
will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state.
the default value is readable.
Chapter 5.14.11.3
for more details about the PWROK pin functionality.
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet