NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 638

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.1.23
18.1.24
638
®
High Definition Audio Controller Registers (D27:F0)
PCS—Power Management Control and Status Register
(Intel
Address Offset:
Default Value:
MID—MSI Capability ID Register
(Intel
Address Offset:
Default Value:
31:24
21:16
14:9
15:8
Bit
7:2
1:0
Bit
7:0
23
22
15
8
®
®
Data — RO. Does not apply. Hardwired to 0.
Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.
B2/B3 Support — RO. Does not apply. Hardwired to 0.
Reserved.
PME Status (PMES) — R/WC.
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel High Definition Audio controller would normally assert the PME#
This bit in the resume well and only cleared on a power-on reset. Software must not make
assumptions about the reset state of this bit and must set it appropriately
Reserved
PME Enable (PMEE) — R/W.
0 = Disable
1 = when set and if corresponding PMES also set, the Intel High Definition Audio controller sets the
This bit in the resume well and only cleared on a power-on reset. Software must not make
assumptions about the reset state of this bit and must set it appropriately
Reserved
Power State (PS) — R/W. This field is used both to determine the current power state of the Intel
High Definition Audio controller and to set a new power state.
00 = D0 state
11 = D3
Others = reserved
NOTES:
Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability structure.
Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability
1. If software attempts to write a value of 01b or 10b in to this field, the write operation must
2. When in the D3
3. When software changes this value from D3
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
complete normally; however, the data is discarded and no state change occurs.
available, but the I/O and memory space are not. Additionally, interrupts are blocked.
is generated, and software must re-initialize the function.
signal independent of the state of the PME_EN bit (bit 8 in this register)
AC97_STS bit in the GPE0_STS register (PMBASE +28h). The AC97_STS bit is shared by AC
’97 and Intel High Definition Audio functions since they are mutually exclusive.
HOT
54h
00000000h
60h
7005h
state
HOT
states, the Intel High Definition Audio controller’s configuration space is
Intel
Description
Description
®
HOT
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
state to the D0 state, an internal warm (soft) reset
32 bits
RO
16 bits
RO, R/W, R/WC