NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 495

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Bit
7
6
5
4
3
2
1
0
Device Interlock Status (DIS) — R/WC. When set, indicates that a platform interlock switch has
been opened or closed, which may lead to a change in the connection state of the device.This bit is
only valid in systems that support an interlock switch (CAP.SIS [ABAR+00:bit 28] set).
For systems that do not support an interlock switch, this bit will always be 0.
Port Connect Change Status (PCS) — RO . This bit reflects the state of PxSERR.DIAG.X.
(ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when
PxSERR.DIAG.X is cleared.
0 = No change in Current Connect Status.
1 = Change in Current Connect Status.
Descriptor Processed (DPS) — R/WC . A PRD with the I bit set has transferred all its data.
Unknown FIS Interrupt (UFS) — RO . When set to ‘1’ indicates that an unknown FIS was
received and has been copied into system memory. This bit is cleared to ‘0’ by software
clearing the PxSERR.DIAG.F (ABAR+130h/1D0h/230h/2D0h, bit 25) bit to ‘0’. Note that this bit
does not directly reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an
unknown FIS is detected, whereas this bit is set when the FIS is posted to memory. Software should
wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may become out of sync.
Set Device Bits Interrupt (SDBS) — R/WC . A Set Device Bits FIS has been received with the I bit
set and has been copied into system memory.
DMA Setup FIS Interrupt (DSS) — R/WC . A DMA Setup FIS has been received with the I bit set
and has been copied into system memory.
PIO Setup FIS Interrupt (PSS) — R/WC . A PIO Setup FIS has been received with the I bit set, it
has been copied into system memory, and the data related to that FIS has been transferred.
Device to Host Register FIS Interrupt (DHRS) — R/WC . A D2H Register FIS has been received
with the I bit set, and has been copied into system memory.
Description
SATA Controller Registers (D31:F2)
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