NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 750
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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Electrical Characteristics
750
Table 22-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 2 of 2)
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment
2. See the AT Attachment
Sym
t96a
t96b
t98a
t98b
ATAPI
measuring these timing parameters.
t93
t94
t95
t97
t99
–
Unlimited Interlock Time (Tui)
STROBE output released-to-
driving to the first transition of
critical timing (Tzfs)
Data Output Released-to-
Driving Until the First Transition
of Critical Timing (Tdzfs)
Maximum time allowed for
output drivers to release (from
asserted or negated) (Taz)
Drivers to assert or negate (from
released) (Tzad)
Ready-to-final-STROBE time
(no STROBE edges shall be
sent this long after negation of
DMARDY#) (Trfs)
Maximum time before releasing
IORDY (Tiordyz)
Minimum time before driving
IORDY (see Note 2) (Tziordy)
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender
terminates a burst) (Tss)
6) specification name.
Parameter 1
–
6 with Packet Interface (ATA/ATAPI
20.0
Min
50
0
0
–
0
–
–
0
Mode 3
(ns)
Intel
Max
10
60
20
–
–
–
–
–
–
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Min
6.7
50
0
0
–
0
–
–
0
Mode 4
(ns)
–
6) specification for further details on
Max
10
60
20
–
–
–
–
–
–
Min
35
25
50
–
–
–
0
0
0
Mode 5
(ns)
–
6 with Packet Interface (ATA/
Max
10
50
20
–
–
–
–
–
–
Measuring
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Location
Sender
Sender
Sender
Device
Note 2
Device
Device
Device
Host
Figure
22-12
22-11
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