NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 225

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.21.7.2.1
5.21.7.3
Intel
Table 5-55. Host Notify Format
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: An external microcontroller must not attempt to access the ICH6’s SMBus Slave logic until at least
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit
Write bit sequence. When the ICH6 detects that the address matches the value in the Receive Slave
Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9)
and signal an Acknowledge during bit 10. In other words, if a Start
is illegal for SMBus Read or Write protocol), and the address matches the ICH6’s Slave Address,
the ICH6 will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start
sequence beginning at bit 20. Once again, if the Address matches the ICH6’s Receive Slave
Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave
Read cycle.
1 second after both RTCRST# and RSMRST# are de-asserted (high).
Format of Host Notify Command
The ICH6 tracks and responds to the standard Host Notify command as specified in the System
Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed
to 0001000b. If the ICH6 already has data for a previously-received host notify command that has
not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it
will NACK following the host address byte of the protocol. This allows the host to communicate
non-acceptance to the master and retain the host notify address and data values for the previous
cycle until host software completely services the interrupt.
reads of the address and data registers.
Table 5-55
17:11
27:20
36:29
Bit
8:2
10
18
19
28
37
38
1
9
Start
SMB Host Address — 7 bits
Write
ACK (or NACK)
Device Address – 7 bits
Unused — Always 0
ACK
Data Byte Low — 8 bits
ACK
Data Byte High — 8 bits
ACK
Stop
shows the Host Notify format.
Description
External Master
External Master
External Master
External Master
External Master
ICH6
External Master
ICH6
External Master
ICH6
External Master
Intel
Driven By
®
ICH6
Always 0001_000
Always 0
ICH6 NACKs if HOST_NOTIFY_STS is 1
Indicates the address of the master; loaded into
the Notify Device Address Register
7-bit-only address; this bit is inserted to complete
the byte
Loaded into the Notify Data Low Byte Register
Loaded into the Notify Data High Byte Register
–
Address
Comment
Functional Description
–
Address
–
Read occurs (which
–
Read
–
Address
225
–