NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 223

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.21.7.2
Intel
Table 5-52. Command Types (Sheet 2 of 2)
Table 5-53. Read Cycle Format
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Format of Read Command
The external master performs Byte Read commands to the ICH6 SMBus Slave I/F. The
“Command” field (bits 18
contain the value that should be read from that register.
Table 5-54
Command
27:21
37:30
18:11
9–FFh
8:2
Bit
10
19
20
28
29
38
39
Type
1
9
8
shows the register mapping for the data byte.
Start
Slave Address - 7 bits
Write
ACK
Command code - 8 bits
ACK
Repeated Start
Slave Address - 7 bits
Read
ACK
Datay Byte
NOT ACK
Stop
SMLINK_SLV_SMI. When ICH6 detects this command type while in the S0 state, it sets the
SMLINK_SLV_SMI_STS bit (see
system is in an S0 state. If the message is received during S1–S5 states, the ICH6
acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set.
NOTE: It is possible that the system transitions out of the S0 state at the same time that the
Reserved
Description
SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit
may get set but not serviced before the system goes to sleep. Once the system returns
to S0, the SMI associated with this bit would then be generated. Software must be able
to handle this scenario.
:
11) indicate which register is being accessed. The Data field (bits 30
External Microcontroller
External Microcontroller
External Microcontroller
Intel
External Microcontroller
ICH6
External Microcontroller
External Microcontroller
External Microcontroller
ICH6
ICH6
External Microcontroller
External Microcontroller
®
ICH6
Driven by
Section
Description
10.9.5). This command should only be used if the
Table 5-53
Must match value in Receive Slave
Address register
Always 0
Indicates which register is being
accessed See
Must match value in Receive Slave
Address register
Always 1
Value depends on register being
accessed. See
shows the Read Cycle Format.
Functional Description
Comment
Table 5-54
Table 5-54
:
37)
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