NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 418

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.3.13
418
Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH6 will cause an SMI# (except
SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
bits 8 – 10 and 12, which do not need enable bits since they are logic ORs of other registers that
have enable bits). The ICH6 uses the same GPE0_EN register (I/O address: PMBase+2Ch) to
enable/disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it
owns the entire GPE0_EN register per ACPI spec. Problems arise when some of the general-
purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs are enabled
for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input signals that are not
indicated as SCI general-purpose events at boot, and exit from sleeping states. BIOS should define
a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.
31:20
Bit
21
20
19
18
17
16
15
14
13
Reserved
MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the SMI. This will occur
when the processor or a bus master accesses an assigned register (or a sequence of accesses).
See
PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due to a PCI Express
PME event or Hot-Plug event.
Reserved
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status
bits in the Intel-Specific USB2 SMI Status Register ANDed with the corresponding enable bits. This
bit will not be active if the enable bits are not set. Writes to this bit will have no effect.
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status
bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will
not be active if the enable bits are not set. Writes to this bit will have no effect.
SMBus SMI Status (SMBus_SMI_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least
1 = Indicates that the SMI# was caused by:
SERIRQ_SMI_STS — RO.
0 = SMI# was not caused by the SERIRQ decoder.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit
TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event.
Section 7.1.32
15.63 us after the initial assertion of this bit before clearing it.
1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and
4. The ICH6 detecting the SMLINK_SLAVE_SMI command while in the S0 state.
(PMBASE + 30h, bit 14) is also set, the ICH6 generates an SMI#.
SMBALERT_DIS bit is cleared, or
the SMB_SMI_EN bits are set, or
PMBASE + 34h
00000000h
No
Core
thru
Section 7.1.35
for details on the specific cause of the SMI.
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Usage:
32-bit
RO, R/WC
ACPI or Legacy