NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 469

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.1.24
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when
SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2)
Address Offset:
Default Value:
the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise
noted.
15:14
13:12
11:10
Bit
9:8
7:6
5:4
3:2
1:0
Reserved
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
Reserved
Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
Reserved
Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
Reserved
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
SCB1 = 0 (33 MHz clk)
SCB1 = 0 (33 MHz clk)
PCB1 = 0 (33 MHz clk)
PCB1 = 0 (33 MHz clk)
11 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
4A
0000h
–
4Bh
SCB1 = 1 (66 MHz clk)
SCB1 = 1 (66 MHz clk)
PCB1 = 1 (66 MHz clk)
PCB1 = 1 (66 MHz clk)
00 = Reserved
00 = Reserved
00 = Reserved
00 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Description
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W
16 bits
FAST_SCB1 = 1 (133 MHz clk)
FAST_SCB1 = 1 (133 MHz clk)
FAST_PCB1 = 1 (133 MHz clk)
FAST_PCB1 = 1 (133 MHz clk)
01 = CT 3 clocks, RP 16 clocks
01 = CT 3 clocks, RP 16 clocks
01 = CT 3 clocks, RP 16 clocks
01 = CT 3 clocks, RP 16 clocks
00 = Reserved
10 = Reserved
00 = Reserved
10 = Reserved
00 = Reserved
10 = Reserved
00 = Reserved
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
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