NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 779

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

24
24.1
Intel
Figure 24-1. XOR Chain Test Mode Selection, Entry and Testing
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Testability
XOR Chain Test Mode Description
The Intel
mode when the chip is not operating in its normal manner. The XOR Chain Mode is entered as
indicated in the following figure:
Notes: RSMRST#, PWROK, RTCRST#, LAN_RST# must be held high during test mode and output testing.
Chain 4 Combination Option:
TP3 / GPIO25
For chains 4 and 5, all PETx[n] signals (of that chain) must be driven during testing.
PCICLK & DMI_CLK should be approximately 1 MHz while running/toggling
ACZ_SDOUT /
RSMRST# /
LAN_RST#
®
EE_DOUT
REQ[4:1]#
REQ[4:1]# = 0000
REQ[4:1]# = 0001
REQ[4:1]# = 0010
REQ[4:1]# = 0011
REQ[4:1]# = 0100
RTCRST#
DMI_CLK
PCICLK
PWROK
If LAN_RST# = 0 during testing (XOR Output Enabled) then Chains 4-1 and 4-2 are separate.
If LAN_RST# = 1 during testing then Chains 4-1 and 4-2 are combined with output on PLTRST#.
LAN_RST# must be high for all other chains
REQ# Settings
ICH6 supports XOR Chain test mode. This non-functional test mode is a dedicated test
XOR Chain Test Mode Selection, Entry and Testing
5ms 10ms
Chain Select (1-5)
Held Low
DMI_CLKp = ‘0’
DMI_CLKn = ‘1’
Run 120 ms
XOR Chain
XOR 1
XOR 2
XOR 3
XOR 4
XOR 5
Run 2 ms
Toggle
XOR Output Enabled
See Note on
Chain 4
Option
Testability
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