NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 649

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

18.1.49
18.2
Intel
Table 18-2. Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
L1ADDU—Link 1 Upper Address Register
(Intel
Address Offset:
Default Value:
Intel
Configuration Registers
(Intel
The base memory location for these memory mapped configuration registers is specified in the
HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The individual registers are then
accessible at HDBAR + Offset as indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
(Intel
D27:F0) (Sheet 1 of 4)
HDBAR +
31:0
Bit
0C–0Dh
0E–0Fh
4A–4Bh
08–0Bh
00–01h
04–05h
06–07h
10–11h
20–23h
24–27h
30–33h
34–37h
40–43h
44–47h
48–49h
Offset
4Ch
02h
03h
®
®
High Definition Audio
®
®
High Definition Audio PCI Register Address Map
Link 1 Upper Address — RO. Hardwired to match the RCBA register value in the PCI-LPC bridge
(D31:F0:F0h).
®
High Definition Audio Controller—D27:F0)
High Definition Audio Memory Mapped
High Definition Audio— D27:F0)
CORBUBASE
CORBLBASE
STATESTS
Mnemonic
CORBCTL
CORBWP
WAKEEN
CORBRP
WALCLK
OUTPAY
INTSTS
INTCTL
SSYNC
INPAY
GCAP
GSTS
VMAJ
GCTL
VMIN
14Ch
See Register Description
Global Capabilities
Minor Version
Major Version
Output Payload Capability
Input Payload Capability
Global Control
Wake Enable
State Change Status
Global Status
Interrupt Control
Interrupt Status
Wall Clock Counter
Stream Synchronization
CORB Lower Base Address
CORB Upper Base Address
CORB Write Pointer
CORB Read Pointer
CORB Control
Intel
®
High Definition Audio Controller Registers (D27:F0)
Register Name
Description
Attribute:
Size:
RO
32 bits
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Default
003Ch
001Dh
4401h
0000h
0000h
0000h
0000h
0000h
00h
01h
00h
R/W, RO
Access
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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