NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 581

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NH82801FBM S L89K

Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FBM S L89K

Lead Free Status / RoHS Status
Compliant
16
16.1
Intel
Table 16-1. AC ‘97 Audio PCI Register Address Map (Audio—D30:F2)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: Registers that are not shown should be treated as Reserved.
Note: Internal reset as a result of D3
AC ’97 Audio Controller Registers
(D30:F2)
AC ’97 Audio PCI Configuration Space
(Audio—D30:F2)
following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0
transition. All resume well registers will not be reset by the D3
2C–2Dh
1C–1Fh
2E–2Fh
18–1Bh
00–01h
02–03h
04–05h
06–07h
10–13h
14–17h
50–51h
52–53h
54–55h
Offset
3Ch
3Dh
0Ah
0Bh
0Eh
34h
08h
09h
40h
41h
NAMMBAR
Mnemonic
NAMBBAR
HEADTYP
CAP_PTR
PCICMD
MMBAR
PCISTS
INT_PN
MBBAR
INT_LN
SVID
PCID
SCC
BCC
CFG
PCS
DID
RID
VID
SID
PID
PC
PI
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Header Type
Native Audio Mixer Base Address
Native Audio Bus Mastering Base Address
Mixer Base Address (Mem)
Bus Master Base Address (Mem)
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
Interrupt Line
Interrupt Pin
Programmable Codec ID
Configuration
PCI Power Management Capability ID
PC -Power Management Capabilities
Power Management Control and Status
HOT
to D0 transition will reset all the core well registers except the
Register Name
AC ’97 Audio Controller Registers (D30:F2)
HOT
to D0 transition.
See register
See register
00000001h
00000001h
00000000h
00000000h
description
description
Default
C9C2h
266Eh
8086h
0000h
0280h
0000h
0000h
0001h
0000h
01h
04h
00h
50h
00h
09h
00h
00
R/W, R/WC
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
Access
R/WO
R/WO
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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